The present invention relates to a CMOS image sensor; and, more particularly, to a unit pixel in a CMOS image sensor with a capacitor coupled photodiode to enhance its capacitance.
A complementary metal oxide semiconductor(CMOS) image sensor is a device that converts an optical image to an electrical signal using a CMOS manufacturing technology, which employs a switching scheme of MOS transistor for transportation of photo-electric charge from photodiode to output node as well as detection of output signal at the output node. In contrast with a charge coupled device (CCD) image sensor currently available in the marketplace, the CMOS image sensor has the following merits; its driving scheme is simplified and various scanning schemes may be implemented; it allows a signal processing circuit to be integrated on a single chip thereby minimize products; it employs therein an interchangeable CMOS technology to be able to lower production costs and low power consumptions.
Referring to FIG. 1, there is shown a connection diagram of a unit pixel in a conventional CMOS image sensor, which has been proposed by the applicant. In FIG. 1, a unit pixel in CMOS image sensor includes one photodiode (PD) and four NMOS transistors. The four transistors include a transfer transistor (TX) for transferring photo electric charges generated from the photodiode to a floating sensing node, a reset transistor (RX) for discharging the charges stored in the floating sensing node to detect subsequent signals, a drive transistor (DX) acting as a source follower, and a select transistor (SX) acting as a switching to an addressing.
The transfer transistor (TX) and the reset transistor (RX) are made of an native NMOS transistor having extremely low threshold voltage nearly equal to zero volt to prevent the degradation of charge transfer efficiency, which may be incurred by the loss of electric charges associated with the voltage drop resulting from the positive threshold voltage of the transistor. Provided between an output OUT of the unit pixel and a ground GND is a load transistor VB for biasing. The photodiode PD and a substrate of the floating sensing node are grounded. In FIG. xe2x80x9cCFxe2x80x9d represents a capacitance of the floating sensing node and xe2x80x9cCPxe2x80x9d represents a capacitance of a pinned photodiode.
Referring to FIG. 2, there is shown a sectional view of a unit pixel in the conventional CMOS image sensor, which has been proposed by the applicant. In FIG. 2, a p+-silicon substrate, a p-epitaxial layer, a p-well, a field oxide film, a gate oxide film, a gate electrode, an N-diffusion region, Pxc2x0 diffusion region, N+-floating diffusion region and an oxide spacer film are depicted by reference numerals 1 to 10, respectively. Referring to FIG. 2, the photodiode PD includes a PNP junction structure, which is formed by the sequential ion implantation of N-type and P-type dopants, or vice versa, into the P-epitaxial layer 2, the Nxe2x88x92-diffusion region 7 and the Pxc2x0 diffusion region 8, wherein the capacitance CP of the photodiode PD is formed by the Nxe2x88x92-diffusion region 7 and the capacitance CF of the floating sensing node is formed by the floating diffusion region FD, i.e., a portion at which one end of the transfer transistor (TX) and one end of the reset transistor (RX) are commonly coupled.
The unit pixel in the image sensor fabricated thus is operated as follows. First, the reset transistor (RX), the transfer transistor (TX) and the select transistor (SX) are turned on to reset the unit pixel. As such, the Nxe2x88x92-diffusion region 7 gradually begins to be depleted and is completely depleted. In this situation, the capacitance CP entails a carrier charging up to a pinning voltage on the completed depletion, and the capacitance CF of the floating sensing node entails a carrier charging up to a supply voltage VDD. Thereafter, the transfer transistor (TX) is turned off, the select transistor (SX) is turned on and then the reset transistor (RX) is turned off. In this situation, an output voltage V1 is generated from the output terminal OUT and stored in a buffer (not shown). Next, the transfer transistor (TX) is turned on to move carriers in the capacitance CP which has been changed according to a light intensity, to the capacitance CF. After that, an output voltage V2 is generated from the terminal OUT and an analog data for V1-V2 is converted to a digital data. Thus, one operation period for the unit pixel is terminated.
As mentioned above, each unit pixel constituting the CMOS image sensor includes the photodiode in which electrons are generated by light incident externally and stored therein, and a circuit for receiving the electrons stored in the photodiode and converting the same to electrical output signals (voltages or currents). In this case, since a maximum output signal is directly proportional to the number of electrons to be extracted from the photodiode, the maximum output signal increases with increased electron acceptability, i.e., an increased capacitance, of the photodiode. In general, a silicon based photodiode is fabricated using a PN junction, and a duplex structure such as PNP or NPN junctions, wherein the electrons containing performance (electron capacity) of these junctions depend on the doping level of silicon substrate itself and the concentration profile of the dopants implanted into the substrate to form the junction. In case the photodiode does not have sufficient capacitance, a certain portion of the photo-electrons which cannot be stored in the photodiode may leak out toward the substrate thereby decrease the maximum output signal and entails an additional problem such as noise generation by the leaked electrons.
Therefore, a sufficient capacitance of the photodiode is of importance. Unfortunately, however, since the capacitance of the photodiode strongly depends on the doping profile of the photodiode which is determined by the implantation conditions of N-type and P-type dopants, it is very difficult to adjust the capacitance of the photodiode at its option.
FIG. 3A is a top view of the conventional unit pixel, which depicts a substantial size of the photodiode and its status, wherein only the photodiode and a gate of the transfer transistor (TX) and the floating sensing node (FD) are schematically shown. FIG. 3B is a sectional view of the conventional unit pixel as taken along the line A-Axe2x80x2 of FIG. 3A.
It is, therefore, a primary object of the present invention to provide a unit pixel in a CMOS image sensor, which is capable of enhancing the capacitance of photodiode to reduce noises and increasing the maximum output signal of the image sensor.
In accordance with a preferred embodiment of the present invention, there is provided a CMOS image sensor, comprising: a photodiode aligned with an edge of an insulating film for separating elements and formed by doping impurities into a semiconductor layer by an ion implantation; and a capacitor formed along with interface between the photodiode and the insulating film on plan and formed by layering a bottom electrode, a dielectric and an upper electrode contacted with the photodiode.